1. Field of the Invention
The invention relates generally to a delay-locked loop (DLL), and more particularly, to a DLL capable of preventing a false lock.
2. Description of Related Art
FIG. 1 is a schematic diagram of a conventional DLL 100. A DLL 100 receives an external reference clock signal FREF and outputs an output clock signal CKOUT for an internal circuit. The DLL 100 includes a phase detector 110, a loop filter 120, and a delay chain 130. The phase detector 110 outputs a comparison signal CMP according to a comparison between the reference clock signal FREF and the output clock signal CKOUT. The delay chain 130 generates the output clock signal CKOUT by delaying the reference clock signal FREF. The loop filter 120 is a low-pass filter capable of filtering noise from the comparison signal CMP and simultaneously controlling a delay time of the output clock signal CKOUT according to the comparison signal CMP.
An ideal DLL locks the output clock signal CKOUT to lag one cycle after the reference clock signal FREF. In other words, the loop filter 120 should control the delay chain 130 so the length of the delay time of the output clock signal CKOUT is set at one cycle. However, since the initial delay of the delay chain when the circuit is turned on is not a fixed value, a false lock results if an initial non-ideal delay occurs.
An operable delay range of the conventional DLL is from 0.5 T to 1.5 T as shown in FIG. 2, in which T is a cycle of the reference clock signal FREF. That is to say, as long as the initial delay time of the clock output clock signal CKOUT relative to the reference clock signal FREF is between 0.5 T and 1.5 T, as shown by CKOUT in FIG. 2, the DLL 100 correctly locks the delay time of the output clock signal CKOUT at 1 T. Besides generating the output clock signal CKOUT, the delay chain 130 also generates five strobe clock signals PHS for the internal circuit. Moreover, if the delay time of the output clock signal CKOUT is x, then the delay times of the five strobe clock signals are 0, (¼)x, (½)x, (¾)x, and x, respectively. FIG. 3 depicts the reference clock signal FREF and an output clock signal CKOUT-1 correctly locked at 1 T. Since the output clock signal CKOUT-1 is locked at the correct delay time, the five strobe clock signals generated by the delay chain are also accurate.
When the initial delay time of the clock output clock signal CKOUT relative to the reference clock signal FREF is outside the range between 0.5 T to 1.5 T, a false lock occurs. As shown in FIG. 2, when the initial delay time of the output clock signal CKOUT is between 1.5 T and 2.5 T, a lock occurs at 2 T. Moreover, when the initial delay time of the output clock signal CKOUT is between 2.5 T and 3.5 T, a lock occurs at 3 T, and so on. A false lock caused by an initial delay time of the output clock signal CKOUT that is greater than 1.5 T is referred to as a harmonic lock, and incorrect strobe clock signals results from the harmonic clock. As shown in FIG. 3, the output clock signal CKOUT-2 is incorrectly locked at 2 T. Due to the fixed proportional relationship of the delay time, the five strobe clock signals PHS-2 corresponding to the output clock signal CKOUT-2 are incorrect and unusable. The output clock signal CKOUT-3 is incorrectly locked at even later integral cycles, and thus the five strobe clock signals PHS-3 corresponding thereto are also inaccurate.
As shown in FIG. 2, when the initial delay time of the output clock signal CKOUT is less than 0.5 T, a lock tends to occur at 0 T. This type of false lock is referred to as a stuck lock, and incorrect strobe clock signals are generated by the delay chain due to the stuck lock.
The two faulty phenomena of the harmonic lock and the stuck lock are referred to as the false lock.